All FM stereo receivers must perform three functions. First, the decoder must detect and lock onto the 19 kHz pilot signal that is added to the FM composite for synchronization of the transmitter and receiver. This synchronization is accomplished with a PLL. Once locked, the decoder is in sync with the transmitted signal and the second function is performed, namely to multiply the FM composite signal by a 38 kHz signal that is in phase with the original 19 kHz pilot. This multiplication process brings the "Left-Right" signal down to the base band (0-15 kHz) making it possible to separate the "Left+Right" and the "Left-Right" information with simple low-pass filters. Thirdly, these signals are summed and differenced to give the desired "Left" and "Right" information reproduced at the speakers of a FM stereo receiver.
The accuracy and noise characteristics of the PLL are very important. Any noise on the 38 kHz signal generated in the PLL will appear in the "Left-Right" signal path. The noise in the signal path is an important measure of the decoder performance and must be minimized. Any inaccuracies in the PLL will cause the gain of the two signal paths to be mismatched. Gain mismatch will cause some "Left(Right)" channel information to be present on the "Right(Left)" output. The parameter called "separation" is a measure of how well the decoder separates the "Left" and "Right" signals and is therefore a benchmark for decoder performance.
A standard PLL is shown in FIG. 1. It is comprised of a phase detector 10, a loop filter 12, a VCO 14, and a frequency divider 16. In an analog system, the phase detector generates a voltage proportional to the difference in the phase between the output of frequency divider 16 and the system input. This voltage is fed through the loop filter 12 and then to the input of the VCO 14. When the VCO output is in phase with the incoming signal, the output of the phase detector 10 stops moving. If the frequency divider 16 is a divide by 2 and the PLL is locked to 19 kHz, the VCO output is 38 kHz, which is required in the decoder signal path.
Analog PLL's have analog VCO's which are inaccurate and are temperature dependent. Costly external components are required, and the bandwidth of the PLL must be widened to account for temperature variation, thereby reducing system performance. In a digital system, the operation of the circuitry is much the same except digital words are used instead of analog voltages. One such digital PLL is disclosed in U.S. Pat. No. 4,577,163. Digital PLL's have digital VCO's, the output frequency of which is controlled by an input bit pattern. The free running frequency of the PLL is very accurate, but the VCO output can only move in quantized steps of frequency. This frequency out is close to correct on the average, but at any one instant in time it may be incorrect. This quantization causes phase error which limits the performance of the FM stereo decoder.